Kshitiz Tyagi

Kshitiz Tyagi graduating from IIT Kanpur, Branch- Ee (Bt-Mt Dual Degree) department as a Graduate (B.Tech) in 2020 has been placed as Hardware engineer in Intel.

a) Other companies that I was shortlisted for: Google Hardware, Texas Instruments (Analog engineer profile) b) Analysis of available options (based on profile, growth, compensation, Brand Name, etc) 1. Google Hardware: This was an attractive opportunity as it scored high on the brand-name, compensation, and profile; as my objective was to secure a job in the electronics core sector, specifically in circuit design related roles. 2. Intel: They offered options of two different roles: (i) architecture research scientist, and (ii) hardware design engineer. I was more interested in the architecture research position, as it was a research-intensive job with nice compensation, on par with the Google offer. The company is the world’s biggest in the semiconductor market, thus its brand-name is also strong. Eventually, they offered me the hardware design position, which was in line with my interests but pay was much less compared to the research engineer profile. 3. Texas Instruments: offered interesting roles related to circuit design, thus capturing my interest. Brand-name is good in the electronics sector. Compensation was decent, though lower than that offered by Google and Intel research engineer positions.

1. Revised the fundamentals of microelectronics through EE210, EE370. PG courses like EE610, and EE619 also helped. 2. Solved previous years placement related tests of various core electronics companies. This gave a good feel of areas where I was weak in, thus I could focus more on these areas in my preparation. 3. Prepared for generic HR related questions in the days leading up to the interviews.

1. Google: First, all applicants had to take a preliminary test, which took place over a Google forms based multi-choice questionnaire, and lasted 45 minutes. The questions were mostly based on fundamentals of digital electronics, such as those covered in EE370 and EE619. Some of the questions were framed in a tricky manner, and required the use of logic, intuition, and basic electronics knowledge. Although I do not know the precise details of the interview shortlisting process, the list of shortlisted candidates was relatively small (around 12-15 students), and seemed to be based on both the performance in the test (scores not revealed), and the submitted resumes. I had three rounds of interviews: in the first, I was asked questions pertaining to mostly digital circuit problems like K-map simplification, questions on blocks like inverters, and one programming related problem on gray codes (interviewer helped explain the exact problem). In the second round, I was asked a long question, based on a networking protocol which the interviewer described in detail. There was another question related to the programming of a ternary search tree, and one HR related question (on the themes of teamwork). The final round also involved technical questions, this time based on timing problems in sequential digital circuits. All rounds lasted roughly 40-45 minutes. 2. Intel: There was a test for the hardware engineer role, while the shortlisting for the research engineer role was based on just the submitted resumes. The test for hardware engineering had 3 sections, one based on aptitude, one based on digital and analog design fundamentals, and the final section involved 2 long, subjective answer type questions which were digital design related. There were two interviews: one each for the research engineer and the hardware engineer roles. Both lasted about 30 minutes. The research engineer interview was pretty generic, there were not any technical questions. The questions were related to some projects I had listed in my resume, and how they have prepared me for a career in research. Other questions were based on what kind of research I would want to be part of at Intel, and I got the opportunity to ask a couple questions about the role as well. In the hardware engineer interview, a lot of questions relating to the basic device and circuit characteristics of a simple CMOS inverter were asked. There was a problem related to debugging and checking Verilog code as well. 3. Texas Instruments: There was a single test, based on which the interview shortlisting took place. Test involved some general aptitude problems, tricky questions related to basic R-C, R-L circuits, and network analysis. There were also some problems based on digital building blocks. There was one technical interview round, wherein thorough questions were asked, relating to OPAMP based feedback circuits, R-C charging, and active circuits. All problems were sophisticated and required a good understanding of fundamentals of analog design. There was a further telephonic interview, with the recruiting HR manager, lasting about 10 minutes. This interview involved the generic HR questions about my interests, and alternative plans (like higher studies).

The general advice would be to take the tests seriously, prepare well by going over past years’ repositories, and working on areas where one might me relatively weak. For interviews, try to polish communication skills and temperament.

Final Tips :
There will be many opportunities in the placement process, it is important to not be overly affected by some early setbacks. Keep good faith in yourself, getting placed is in most cases easier than how most rate it to be.